1. Field of the Invention
The present invention relates to a memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughput. In particular, the invention relates to a method and a memory circuit capable of ensuring correct reading of the memory with improved performance with respect to conventional methods and circuits.
2. Discussion of the Related Art
In fast parallel memories, one of the most challenging problems is the error of a generic read operation caused by any source of noise, whether internal to the memory device or caused by the memory itself during the switching of its output buffers.
This problem worsens as the degree of parallelism (x8, x16, x32, . . . ) increases and as the required transition speed rises.
Switchings on the outputs, in addition to generating intense noise on the internal circuits of the memory, generally slow down the reading times; the less synchronously this event occurs and the greater the number of outputs, the greater the slowing effect.
Accordingly, memories with a plurality of outputs are vulnerable to noise, and it is difficult to improve their speed performance.
A possible answer to this problem is a design approach with so-called time-controlled architectures, in which a time is set during which reading must be performed.
However, this solution has further problems. First of all, there is the drawback of the difficulty in achieving correct reading at power supply start-up, i.e., when the power supply has not yet reached its steady-state value.
In a time-controlled or sampled system, once a reading operation has been performed, it cannot be changed until the next reading operation occurs.
Furthermore, this second type of memory architecture does not have the necessary features of flexibility and adaptability to the various conditions of the devices of the memory and to the different power supply conditions. The adoption of a rigid architecture does not combine well with the indispensable requirement of matching the conditions and properties of the devices and circuits and with the need to optimize the reading speed in every circumstance while preserving its correctness.
This entails the need to determine preset delays to ensure reading correctness; these delays must also be long enough to be sure of having correct reading in all possible operating situations and with devices having different characteristics; however, the problem of first reading is still not solved.
The lack of flexibility and adaptability makes it difficult to use these architectures if the technology used in the memory changes, unless one radically modifies the circuital structure of the architecture to adapt to the new requirements.
Further drawbacks are caused by the consumption of the memory circuits and by reliability problems, caused by the fact that the read circuits are constantly biased.